[Openmcl-devel] 32 bit lisp

martin brooks.martin at sympatico.ca
Thu Feb 1 18:55:36 PST 2018


Parallelism and accelerators are a terrific opportunity for CL.
For example, one could run CL as an OpenCL host, with FFI to the OpenCL host C library, so that lisp creates and coordinates work on GPU and FPGA.

Although Nvidia & CUDA are dominant now, the race has only begun.
Risk-V, exciting!
Or how about https://www.allaboutcircuits.com/news/intel-to-introduce-new-cpu-fpga-hybrid-chip-supported-by-acceleration-stack/ <https://www.allaboutcircuits.com/news/intel-to-introduce-new-cpu-fpga-hybrid-chip-supported-by-acceleration-stack/> ?
All future systems will use parallel accelerators.


> On Feb 1, 2018, at 9:10 PM, R. Matthew Emerson <rme at acm.org> wrote:
> 
> 
> 
>> On Feb 1, 2018, at 4:31 PM, martin <brooks.martin at sympatico.ca> wrote:
>> 
>> I’d like to offer a future perspective — where lisp is running on a small cpu in a system on a chip.
>> SoC’s today offer ARM, Intel and other CPUs as hard IP; we should anticipate CL as a viable development language in future.
>> Or, perhaps less ambitious, CL will run on small CPUs in board-level systems.
>> For CCL releases in that future, various word sizes may be required.
> 
> Certainly the 32-bit ARM port will remain.
> 
> A 64-bit ARM port is, of course, desirable.  I got a replacement Odroid C2 after I fried my earlier unit, so all that is lacking is ambition on my part (and maybe a few bundles of $100 bills).  :-)
> 
> I thought that Intel would have enjoyed more success in the SOC and embedded area, but it seems to me that they just haven't been able to make any inroads there.
> 
> A RISC-V port could be fun.  Now that Western Digital is going to use RISC-V chips in products, it might end up going somewhere.
> 
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