<div dir="auto"><div>The following from intel might be the first to provide access:<div dir="auto"><div dir="auto"><br></div><div dir="auto"><a href="https://www.intel.com/content/www/us/en/developer/articles/tool/software-development-emulator.html">https://www.intel.com/content/www/us/en/developer/articles/tool/software-development-emulator.html</a></div><div dir="auto"><br></div></div>Doesnt support APX yet but does support upto AMX technopogy.<br><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Tue, 25 Jul 2023, 03:10 R. Matthew Emerson, <<a href="mailto:rme@acm.org">rme@acm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><a href="https://www.intel.com/content/www/us/en/developer/articles/technical/advanced-performance-extensions-apx.html" rel="noreferrer noreferrer" target="_blank">https://www.intel.com/content/www/us/en/developer/articles/technical/advanced-performance-extensions-apx.html</a><br>
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Intel plans to increase GPRs to 32, some 3-operand insns, more conditional insns, etc.<br>
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It’d be fun to change CCL to use some of these new features. I have no idea, though, when hardware supporting them will become available.<br>
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