<html><head><meta http-equiv="content-type" content="text/html; charset=utf-8"></head><body dir="auto">Keep in mind—and this has been confirmed by RME himself—that anything you find in the CCL repository related to the arm64 target is an <i>untested</i> <i>sketch</i>. What Matt told me is consistent what I found: that he made a noble, <span style="caret-color: rgb(0, 0, 0); color: rgb(0, 0, 0);">aspirational stab at shifting to a <i>high tags</i> runtime typing scheme, taking advantage of a</span><span style="caret-color: rgb(0, 0, 0); color: rgb(0, 0, 0);"> valuable, <i>documented</i> architectural </span><span style="caret-color: rgb(0, 0, 0); color: rgb(0, 0, 0);">feature: that the arm64 ignores the upper bits of every 64-bit memory address. Then he </span><span style="caret-color: rgb(0, 0, 0); color: rgb(0, 0, 0);">abandoned this approach for reasons of practicality and then, alas, had to move on to other projects.</span><div><span style="caret-color: rgb(0, 0, 0); color: rgb(0, 0, 0);"><br></span></div><div><span style="caret-color: rgb(0, 0, 0); color: rgb(0, 0, 0);">With all due respects to any work in progress, perhaps we should discuss as a group “</span>conventions used by ARM64 assembly code that's already recorded in the main CCL repo (e.g., register names and lisp_frame layout from arm64-constants.s).” Yes, these might be totally fine, but there may be uncaught errors, and these decisions should at least be reviewed by extra eyeballs before we build a large body of work on them. I have already spotted typos in the checked-in, arm64 instruction tables. We plan to check in better tables from a verified source plus a work-in-progress disassembler. </div><div><br></div><div>As for the complexity of the existing CCL compiler, it’s prudent not be too encouraged by a few isolated experiments. Gary B. is a truly brilliant software engineer. It is well known that he worked largely alone and kept vast troves of undocumented, internal knowledge about the compiler in his head. Common Lisp is a very complicated language for compiler writers to tackle, especially when you consider the myriad of existing performance optimizations, only a subset of which are well-exercised “in the wild.”</div><div><br></div><div>It is my goal to keep the integrity of this magnum opus largely intact. It works. It is stable. Once multiple people start messing with it, we <i>will</i> introduce stealth “corner case” bugs that might remain untested and unfixed for years.</div><div><br></div><div>Franz, which has a larger user community, recently fixed an obscure, but <i>actually used</i>, interaction between the compiler and the GC that caused a commercial application I am well familiar with to crash about once a month. They had to pull one of their top developers out of retirement to isolate and fix the problem. CCL no longer has this luxury. </div><div><br></div><div>We need to be methodical and risk-averse on our path forward. </div><div><div><font color="#000000"><span style="caret-color: rgb(0, 0, 0);"><br id="lineBreakAtBeginningOfSignature"></span></font><div dir="ltr">--Tim</div><div dir="ltr"><br><blockquote type="cite">On Feb 28, 2024, at 20:49, Robert Munyer <2420506348@munyer.com> wrote:<br><br></blockquote></div><blockquote type="cite"><div dir="ltr"><blockquote type="cite"><span>Tim's right: I don't think GB ever got around to figuring out what</span><br></blockquote><blockquote type="cite"><span>registers to use in ARM64.</span><br></blockquote><span></span><br><span>In the parts of the compiler that I've developed so far, I've just</span><br><span>been adhering to conventions used by ARM64 assembly code that's already</span><br><span>recorded in the main CCL repo (e.g., register names and lisp_frame</span><br><span>layout from arm64-constants.s) but nothing's carved in stone,</span><br><span>I can change that stuff pretty easily.</span><br><span></span><br><blockquote type="cite"><span>Here's a bit of information on existing ports collected in one place.</span><br></blockquote><blockquote type="cite"><span></span><br></blockquote><blockquote type="cite"><span>This needs more sanity checking, but I think it's pretty close to accurate:</span><br></blockquote><blockquote type="cite"><span>https://github.com/Clozure/ccl/wiki/Register-Usage-in-CCL-Implementations</span><br></blockquote><blockquote type="cite"><span></span><br></blockquote><blockquote type="cite"><span>And this has been up for a while:</span><br></blockquote><blockquote type="cite"><span>https://github.com/Clozure/ccl/wiki/Arch-Constant-Values-in-CCL</span><br></blockquote><span></span><br><span>Thanks, I will look at those.</span><br><span></span><br><blockquote type="cite"><blockquote type="cite"><span>My current crazy plan is to write a</span><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span>specialized (*) ppc64 to arm64 translator and use it to convert all</span><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span>the subprims (once)</span><br></blockquote></blockquote><span></span><br><span>I don't have an informed opinion about that (not having paid much</span><br><span>attention to subprimitives yet) but my initial reaction is that it's</span><br><span>a nice idea that's worth trying.</span><br><span></span><br><blockquote type="cite"><blockquote type="cite"><span>and translate the ppc64 compiler output (on an</span><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span>ongoing basis). I know this isn’t what RME would do, but it seems</span><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span>less risky that doing “open heart surgery” on the compiler.</span><br></blockquote></blockquote><span></span><br><span>I don't think that will be necessary, because the "brain surgery"</span><br><span>is relatively easy. I have found that I can take large functions</span><br><span>from e.g. ppc2.lisp, and make only a few small changes to get them</span><br><span>to work on ARM64 code.</span><br><span></span><br><span>-- Robert Munyer</span><br><span>https://ccl-arm64-2023-07.srht.site</span><br><span></span><br><span>On 25 February 2024, Shannon Spires wrote:</span><br><span></span><br><blockquote type="cite"><span>Tim's right: I don't think GB ever got around to figuring out what</span><br></blockquote><blockquote type="cite"><span>registers to use in ARM64.</span><br></blockquote><blockquote type="cite"><span></span><br></blockquote><blockquote type="cite"><span>Here's a bit of information on existing ports collected in one place.</span><br></blockquote><blockquote type="cite"><span></span><br></blockquote><blockquote type="cite"><span>This needs more sanity checking, but I think it's pretty close to accurate:</span><br></blockquote><blockquote type="cite"><span>https://github.com/Clozure/ccl/wiki/Register-Usage-in-CCL-Implementations</span><br></blockquote><blockquote type="cite"><span></span><br></blockquote><blockquote type="cite"><span>And this has been up for a while:</span><br></blockquote><blockquote type="cite"><span>https://github.com/Clozure/ccl/wiki/Arch-Constant-Values-in-CCL</span><br></blockquote><blockquote type="cite"><span></span><br></blockquote><blockquote type="cite"><span>-SS</span><br></blockquote><blockquote type="cite"><span></span><br></blockquote><blockquote type="cite"><span>On 2/25/24 3:50 PM, Tim McNerney wrote:</span><br></blockquote><blockquote type="cite"><blockquote type="cite"><span>Thanks for doing this experiment, Robert.</span><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span>Gary B., to the best of my knowledge, never tackled designing</span><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span>register conventions or stack usage for the arm64. This is an open</span><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span>problem for the taking. I haven’t yet searched for CCL documentation</span><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span>on register and stack usage on the PPC64. But my own strategy would</span><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span>be to try to map one into the other with very few changes, kinda</span><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span>like the spirit your experiment. My current crazy plan is to write a</span><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span>specialized (*) ppc64 to arm64 translator and use it to convert all</span><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span>the subprims (once) and translate the ppc64 compiler output (on an</span><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span>ongoing basis). I know this isn’t what RME would do, but it seems</span><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span>less risky that doing “open heart surgery” on the compiler.</span><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span></span><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span>(*) by specialized meaning it is not a general translated, but</span><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span>rather designed specifically for CCL hand-written assembly language</span><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span>and compiler output, and knows how to rewrite register references</span><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span>based on knowledge of the register and stack conventions for both</span><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span>targets.</span><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span>--Tim</span><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span></span><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span>On Feb 25, 2024, at 16:05, Robert Munyer <2420506348@munyer.com> wrote:</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span></span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span>I have made some progress toward a CCL-to-ARM64 compiler, by taking</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span>code from the existing CCL-to-PPC64 compiler, and modifying it to emit</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span>ARM64 instruction sequences that resemble ARM64 assembly code that was</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span>checked-in by Gary Byers before 2013-10-22.</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span></span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span>It compiles the body of this function:</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span></span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> (defun fixnum-fibonacci (n)</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> (declare (type (mod 24) n)</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> (optimize (safety 0) (speed 3)))</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> (do ((a 1 b)</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> (b 0 (the fixnum (+ a b)))</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> (n n (1- n)))</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> ((zerop n) b)</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> (declare (fixnum a b n))))</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span></span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span>to this ARM64 machine code:</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span></span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> aa1e03f8 a9bf7bf9 f9402f80 eb2063ff 5400004a d4207d00 f81f8f2f</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> f81f8f30 f81f8f31 f81f8f32 d2800112 d2800010 f9400f31 14000008</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> f81f8f30 8b10024f f81f8f2f d1002231 f9400732 f9400330 91004339</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> f100023f 54ffff01 aa1003ef f9400332 f9400731 f9400b30 a9407bf9</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> aa1803fe 910043ff d65f03c0</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span></span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span>(hand-disassembled here [1]), which, when pasted into this test</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span>program [3], calculates "fibonacci(23) = 28657".</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span></span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span>If you have an Apple Silicon device with Linux and GCC, I think you</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span>should be able to run the test program on it. (Darwin might also</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span>work, with some tweaking.) Paste the program's code [3] into a text</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span>file named test-fib.s, then enter "gcc test-fib.s" and "./a.out".</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span></span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span>For comparison, here is the result of running the existing PPC64</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span>compiler on the same Fibonacci source code: [2].</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span></span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span>Forge resources (source code, wiki wiki, issue tracker, mailing</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span>lists) are available at https://ccl-arm64-2023-07.srht.site .</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span></span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span>Some disclaimers...</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span></span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span>I have not yet made any effort to make the compiled code thread-safe</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span>or signal-safe or garbage-collection-safe, so I wouldn't expect it to</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span>work correctly in a real CCL kernel.</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span></span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span>I mostly have implemented only enough of the compiler for the Fibonacci</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span>function above, so I wouldn't expect other functions to work correctly.</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span></span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span>I don't fully understand how GB intended ARM64 register assignments</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span>and stack discipline to work, so feedback in those areas would be</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span>especially welcome.</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span></span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span>-- Robert Munyer</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span></span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span>[1] --------</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span></span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span>fib (mov loc-pc lr)</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> (stp vsp lr (:-@! sp 16))</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> (ldr imm0 (:+@ rcontext 88))</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> (cmp sp imm0)</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> (b.ge l24)</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> (brk 1000)</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span>l24 (str arg_z (:-@! vsp 8))</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> (str save0 (:-@! vsp 8))</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> (str save1 (:-@! vsp 8))</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> (str save2 (:-@! vsp 8))</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> (mov save2 '1)</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> (mov save0 '0)</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> (ldr save1 (:+@ vsp 24))</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> (b l84)</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span>l56 (str save0 (:-@! vsp 8))</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> (add arg_z save2 save0)</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> (str arg_z (:-@! vsp 8))</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> (sub save1 save1 '1)</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> (ldr save2 (:+@ vsp 8))</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> (ldr save0 (:@ vsp))</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> (add vsp vsp 16)</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span>l84 (cmp save1 '0)</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> (b.ne l56)</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> (mov arg_z save0)</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> (ldr save2 (:@ vsp))</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> (ldr save1 (:+@ vsp 8))</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> (ldr save0 (:+@ vsp 16))</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> (ldp vsp lr (:@ sp))</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> (mov lr loc-pc)</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> (add sp sp 16)</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> (ret)</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span></span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span>[2] --------</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span></span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span>0000000000000000 <fib>:</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> 00: 7d c8 02 a6 mflr loc_pc</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> 04: f8 21 ff e1 stdu sp,-32(sp)</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> 08: fa 01 00 08 std fn,8(sp)</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> 0c: f9 c1 00 10 std loc_pc,16(sp)</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> 10: f9 e1 00 18 std vsp,24(sp)</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> 14: 7e 50 93 78 mr fn,nfn</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> 18: e8 62 00 58 ld imm0,88(rcontext)</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> 1c: 7c 41 18 88 tdllt sp,imm0</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> 20: fa ef ff f9 stdu arg_z,-8(vsp)</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> 24: fb ef ff f9 stdu save0,-8(vsp)</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> 28: fb cf ff f9 stdu save1,-8(vsp)</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> 2c: fb af ff f9 stdu save2,-8(vsp)</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> 30: 3b a0 00 08 li save2,8</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> 34: 3b e0 00 00 li save0,0</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> 38: eb cf 00 18 ld save1,24(vsp)</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> 3c: 48 00 00 20 b 5c <fib+0x5c></span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> 40: fb ef ff f9 stdu save0,-8(vsp)</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> 44: 7e fd fa 14 add arg_z,save2,save0</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> 48: fa ef ff f9 stdu arg_z,-8(vsp)</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> 4c: 3b de ff f8 addi save1,save1,-8</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> 50: eb af 00 08 ld save2,8(vsp)</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> 54: eb ef 00 00 ld save0,0(vsp)</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> 58: 39 ef 00 10 addi vsp,vsp,16</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> 5c: 2c 3e 00 00 cmpdi save1,0</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> 60: 40 82 ff e0 bne 40 <fib+0x40></span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> 64: 7f f7 fb 78 mr arg_z,save0</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> 68: eb af 00 00 ld save2,0(vsp)</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> 6c: eb cf 00 08 ld save1,8(vsp)</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> 70: eb ef 00 10 ld save0,16(vsp)</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> 74: e9 c1 00 10 ld loc_pc,16(sp)</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> 78: e9 e1 00 18 ld vsp,24(sp)</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> 7c: ea 01 00 08 ld fn,8(sp)</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> 80: 7d c8 03 a6 mtlr loc_pc</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> 84: 38 21 00 20 addi sp,sp,32</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> 88: 4e 80 00 20 blr</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> 8c: 83 a9 ff e0 lwz save2,-32(allocptr)</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span></span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span>[3] --------</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span></span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> .global main</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> .extern printf</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> .text</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span></span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span>fmt: .asciz "fibonacci(23) = %ld\n"</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span></span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> .balign 4</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span></span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span>fib: .inst 0xAA1E03F8, 0xA9BF7BF9, 0xF9402F80, 0xEB2063FF, 0x5400004A</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> .inst 0xD4207D00, 0xF81F8F2F, 0xF81F8F30, 0xF81F8F31, 0xF81F8F32</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> .inst 0xD2800112, 0xD2800010, 0xF9400F31, 0x14000008, 0xF81F8F30</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> .inst 0x8B10024F, 0xF81F8F2F, 0xD1002231, 0xF9400732, 0xF9400330</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> .inst 0x91004339, 0xF100023F, 0x54FFFF01, 0xAA1003EF, 0xF9400332</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> .inst 0xF9400731, 0xF9400B30, 0xA9407BF9, 0xAA1803FE, 0x910043FF</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> .inst 0xD65F03C0</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span></span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span>main: mov x0, sp</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> stp fp, lr, [sp, -64]!</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> mov fp, sp</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> stp x24, x25, [sp, -16]!</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> mov x25, x0</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> sub x0, sp, 32</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> stp x0, x28, [sp, -16]!</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> sub x28, sp, 88</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> mov x15, 23 << 3</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> bl fib</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> asr x1, x15, 3</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> adr x0, fmt</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> bl printf</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> ldp x0, x28, [sp], 16</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> ldp x24, x25, [sp], 16</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> ldp fp, lr, [sp], 64</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> mov x0, 0</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span> ret</span><br></blockquote></blockquote></blockquote><span></span><br></div></blockquote></div></div></body></html>